Partial response, maximum likelihood (PRML) recording and playback channels have been implemented within data storage devices, such as hard disk drives. Commonly assigned U.S. Pat. No. 5,341,249 to Abbott, Nguyen and Johnson, entitled: "Disk Drive Using PRML Sampling Data Detection with Digital Adaptive Equalization"; and, the present inventor's commonly assigned, co-pending U.S. patent application Ser. No. 08/276,817 filed on Jul. 10, 1994, entitled: "Real-Time DC Offset Control and Associated Method", now U.S. Pat. No. 5,459,679 provide representative descriptions of the state of the art of partial response, class IV magnetic recording and playback channels. The descriptions thereof are incorporated herein by reference as background.
PRML channels require that the readback signal be correctly equalized, be of a proper amplitude, contain no direct current (DC) offset, and be correctly sampled by an analog to digital converter, in order to realize maximum detector performance. Equalization to a desired spectrum response is typically carried out by analog filtering, or digital finite impulse response (FIR) filtering, or by a combination of analog and digital FIR filtering as was practiced in U.S. Pat. No. 5,341,249 referenced above.
The correct amplitude, DC offset, and sampling time are controlled by digital feedback loops. These loops implement algorithms that compute the amount of amplitude, DC offset and phase error present on the digitized signal samples, and feed back that information either to increase or decrease the amplitude of the signal, its DC content or the required sampling frequency (phase).
The correct amplitude, DC offset, and timing control loops are typically implemented by following known control algorithms. Gain and timing control algorithms are presented in U.S. Pat. No. 5,341,249, and a DC offset control algorithm is presented U.S. patent application Ser. No. 08/276,817, now U.S. Pat. No. 5,459,679 both referenced above.
For example, amplitude error is computed from: EQU .DELTA.g.sub.n =e.sub.n sgn(x.sub.n)
where e.sub.n =x.sub.n -x.sub.n is the signal error, xn is the signal sample value, and x.sub.n is the expected sample value. The amplitude error is then sent through an integrator function to obtain the required correction to the signal amplitude:
G.sub.n+1 =G.sub.n +.gamma..DELTA.g.sub.n
where .gamma. is the gain control loop gain (.ltoreq.1) and G.sub.n is the value of the gain loop correction at time n. As the gain loop adapts, the value of the gain error is minimized to a condition when the value of the gain correction stops changing with time. This condition is known as "convergence" (steady state).
When the gain, timing and DC offset control loop equations are implemented in hardware, the values of the respective gain, timing and DC offset errors are updated every clock cycle n, i.e. which is the sampling rate of the particular detection channel. The higher the channel rate, the more power will be consumed by the control loops. One solution is to compute the gain, timing and DC offset error every other cycle, with a resultant loss of one half of the information and a doubled convergence time as consequences. With this approach convergence time can be improved somewhat at the expense of higher loop noise.
A similar approach was proposed in U.S. Pat. No. 5,341,249 referenced above which called for averaging the timing errors within the timing control loop, and for selecting and putting out every other gain error within the gain control loop. While this approach realized some reduction in power consumption, it is important to note that the timing and gain calculations were carried out at the channel rate, and rate scaling occurred only after the control loop values had already been calculated.
Thus, a hitherto unsolved need has remained for a high speed PRML sampling data detection channel in which the control loops operate effectively at reduced power consumption levels.